A 10-b 200-kS/s 250-nA Self-Clocked Coarse-Fine SAR ADC

A 10-bit ultra-low power SAR implemented in a standard 0.18-μm CMOS technology is described. The architecture consists of a coarse and a fine SAR ADC. The 2-bit coarse SAR presets the two MSB capacitive arrays of the fine SAR, thus avoiding the largest sources of dynamic power consumption. The use of two low resolution comparators in the coarse converter enables compensating for the offset mismatches between the coarse and fine ADCs. The comparator of the fine SAR obtains high sensitivity and very low power thanks to a gain enhanced dynamic pre-amplifier. A loop delay line generates all the phases for the SAR logic and permits three different modes of operation: on-demand, self-clocked, and clocked. In the clocked mode and 200 kS/s, this converter achieves 9.05 bit ENOB while consuming 200 nW. The resulting FoM is 1.88 fJ/conv.-level.